METHOD AND APPARATUS FOR REDUCING READ LATENCY FOR A BLOCK ERASABLE NON-VOLATILE MEMORY

Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional...

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Bibliographic Details
Main Authors GUO, Xin, DAYACAP, Justin R, DOLLER, Joseph F, PELSTER, David J, WAKCHAURE, Yogesh B, RUBY, Paul D, FRICKEY, Robert E
Format Patent
LanguageEnglish
French
German
Published 01.05.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.
Bibliography:Application Number: EP20240164174