METHOD FOR DESIGNING TEST CIRCUIT, AND ELECTRONIC DEVICE
This disclosure relates to a method for designing a test circuit, an apparatus, and a device. The method includes determining a feature of a to-be-tested circuit based on data representing the to-be-tested circuit. The method further includes determining switch distribution for the to-be-tested circ...
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Main Authors | , , , , |
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Format | Patent |
Language | English French German |
Published |
18.09.2024
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Subjects | |
Online Access | Get full text |
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Summary: | This disclosure relates to a method for designing a test circuit, an apparatus, and a device. The method includes determining a feature of a to-be-tested circuit based on data representing the to-be-tested circuit. The method further includes determining switch distribution for the to-be-tested circuit based on the feature of the to-be-tested circuit. The switch distribution represents distribution, in a two-dimensional switch matrix circuit, of a plurality of switches that are in a test circuit and that are coupled to a plurality of scan chains of the to-be-tested circuit. The switch matrix circuit includes a plurality of rows and a plurality of columns, any one of the plurality of rows has at least one of the plurality of switches, and any one of the plurality of columns has at least one of the plurality of switches. In this manner, switch distribution for a low-power control module and a mask control module may be determined, so as to reduce a quantity of scan chains that are additionally enabled in an input phase and improve accuracy of disabling, in an output phase, a scan chain that has an X state, thereby optimizing test power consumption and improving test accuracy. |
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Bibliography: | Application Number: EP20210951327 |