HARDWARE-ASSISTED CORE FREQUENCY AND VOLTAGE SCALING IN A POLL MODE IDLE LOOP

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core i...

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Bibliographic Details
Main Authors UDUPATI, Suresh, PURANDARE, Adwait, NATHAN, Ofer, HUNT, David, VARMA, Ankush, MACNAMARA, Christopher M, SHAH, Pritesh P, GENDLER, Alexander
Format Patent
LanguageEnglish
French
German
Published 01.05.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.
Bibliography:Application Number: EP20220828932