NOVEL DELAY CELL FOR QUADRATURE CLOCK GENERATION WITH INSENSITIVITY TO PVT VARIATION AND EQUAL RISING/FALLING EDGES

A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input...

Full description

Saved in:
Bibliographic Details
Main Authors TANG, Chiu, Keung, CHEN, Zhiqin
Format Patent
LanguageEnglish
French
German
Published 07.02.2024
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Online AccessGet full text

Cover

More Information
Summary:A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.
Bibliography:Application Number: EP20220709933