A CIRCUIT CELL FOR A STANDARD CELL SEMICONDUCTOR DEVICE
The disclosure relates to a circuit cell for a standard cell semiconductor device, comprising:a first and second FET device, each comprising:a source body and a drain body, each comprising a common source or drain body portion and a set of source or drain prongs protruding from the common source or...
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Main Authors | , , |
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Format | Patent |
Language | English French German |
Published |
08.11.2023
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Subjects | |
Online Access | Get full text |
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Summary: | The disclosure relates to a circuit cell for a standard cell semiconductor device, comprising:a first and second FET device, each comprising:a source body and a drain body, each comprising a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion,a set of channel layers, each channel layer extending between a pair of source and drain prongs, anda gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion.The common source and drain body portions of the first FET device are arranged along a first routing track. The common source and drain body portions of the second FET device are arranged along a third routing track. The channel layers of the first and second FET devices are arranged along a second routing track intermediate the first and third routing tracks. The source and drain prongs of the first FET device and the second FET device protrude from the respective common source or drain body portions to define an overlap with the second routing track. The common gate body portion of the first and second FET devices are arranged along the third and first routing track, respectively. The gate prongs of the first and the second FET device protrude from the respective common gate body portions to define an overlap with the second routing track. |
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Bibliography: | Application Number: EP20220171942 |