NON-VOLATIVE MEMORY SYSTEM CONFIGURED TO MITIGATE ERRORS IN READ AND WRITE OPERATIONS

A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memor...

Full description

Saved in:
Bibliographic Details
Main Author OSTERTUN, Soenke
Format Patent
LanguageEnglish
French
German
Published 03.01.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.
Bibliography:Application Number: EP20230165080