CHIP AND ELECTRONIC DEVICE

• Main Authors: GAO, Bo, TANG, Longgu, HU, Fei, LIU, Zhihua, HUANG, Boning, LIU, Chia Fu
• Format: Patent
• Language: English; French; German
• Published: 20.09.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A chip and an electronic device are disclosed, and relate to the field of chip technologies, to reduce a cracking risk of a passivation layer, and improve reliability of the chip. The chip is divided into a main functional area, a transition area, and a protection area, where the transition area is located between the main functional area and the protection area. The chip includes a field oxide, a metal layer, and a passivation layer that are sequentially stacked on a semiconductor substrate. The field oxide and the passivation layer are located in the transition area and the protection area, and the metal layer is located in the main functional area and the transition area. In the transition area, the field oxide includes a primary field oxide and at least one secondary field oxide that are disposed at intervals, and the secondary field oxide is located on a side of the primary field oxide facing the main functional area. In the transition area, the metal layer extends from the main functional area to a side of the primary field oxide facing away from the semiconductor substrate. The passivation layer extends from a side of the metal layer facing away from the semiconductor substrate to a side of the metal layer facing away from the main functional area to cover a surface of the side of the metal layer facing away from the semiconductor substrate and a surface of the side of the metal layer facing away from the main functional area.