SENSE AMPLIFIER ARCHITECTURE FOR A NON-VOLATILE MEMORY STORING CODED INFORMATION

A sense amplifier architecture (10) for a memory device (1) having a plurality of memory cells (3), wherein groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high ('1') or logic low ('0'), of the memory cells of the group; the sen...

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Bibliographic Details
Main Authors DISEGNI, Fabio Enrico Carlo, LO IACONO, Daniele, TOMASONI, Alessandro, CARISSIMI, Marcella
Format Patent
LanguageEnglish
French
German
Published 12.07.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A sense amplifier architecture (10) for a memory device (1) having a plurality of memory cells (3), wherein groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high ('1') or logic low ('0'), of the memory cells of the group; the sense amplifier architecture (10) has: a plurality of sense amplifier reading branches (15), each sense amplifier reading branch (15) coupled to a respective memory cell (3) and configured to provide an output signal (sCOMP_A), which is indicative of a cell current (Icell) flowing through the same memory cell (3); a comparison stage (12), to perform a comparison between the cell currents (Icell) of memory cells (3) of a group; and a logic stage (13), to determine, based on comparison results provided by the comparison stage (12), a read codeword corresponding to the group of memory cells (3). Information may be stored in different subsets (SB1, SB2) of codewords, the sense amplifier architecture (10) in this case having a subset definition circuit (40), to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.
Bibliography:Application Number: EP20220211046