STANDARD CELL ARCHITECTURE WITHOUT POWER DELIVERY SPACE ALLOCATION

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. The integrated circuit comprises a first and a second transistor on the front side of a wafer, but no power deli...

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Bibliographic Details
Main Authors WANG, Xinning, YEMENICIOGLU, Sukru, KOBRINSKY, Mauro J, SCHENKER, Richard E, GHANI, Tahir
Format Patent
LanguageEnglish
French
German
Published 28.06.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. The integrated circuit comprises a first and a second transistor on the front side of a wafer, but no power delivery tracks on the front side of the wafer electrically coupled to the first or second transistor, and no vias delivering power and ground from metal tracks on the back side of the wafer to the front side of the wafer between the first and second transistor. The first and second transistor may be NMOS or PMOS transistors.
Bibliography:Application Number: EP20220201899