HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING

• Main Authors: LIBBERT, Jeffrey Louis, FEI, Lu, KOMMU, Srikanth, THOMAS, Shawn G, WANG, Gang, USENKO, Alex, PEIDOUS, Igor, JONES, Andrew M
• Format: Patent
• Language: English; French; German
• Published: 18.10.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A multilayer structure comprising:a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 Ohm-cm;a semiconductor layer comprising amorphous silicon germanium or polycrystalline silicon germanium, wherein the amorphous silicon germanium or the polycrystalline silicon germanium has a molar percent of germanium of at least about 5 molar %, and further wherein the semiconductor layer comprises dislocations selected from the group consisting of misfit dislocations, threading dislocations, and a combination thereof, wherein a concentration of dislocations is between 1×105/cm2 and 1×1010/cm2, the semiconductor layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate;a dielectric layer comprising a material selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof, the dielectric layer in interfacial contact with the semiconductor layer comprising silicon and germanium; anda single crystal semiconductor device layer in interfacial contact with the dielectric layer.