SYSTEMS, APPARATUSES, AND METHODS FOR FUSED MULTIPLY ADD

In some embodiments, an apparatus with execution circuitry is provided. The execution circuitry is to execute a single instruction to, for each result packed data element: preserve an existing value of the result packed data element or set the result packed data element to zero if a corresponding bi...

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Bibliographic Details
Main Authors Gradstein, Amit, Majcher, Piotr, Girkar, Milind B, Charney, Mark J, Valentine, Robert, Ryvchin, Galina, Corbal, Jesus, Rubanovich, Simon, Ould-Ahmed-Vall, ElMoustapha, Sperber, Zeev
Format Patent
LanguageEnglish
French
German
Published 15.03.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In some embodiments, an apparatus with execution circuitry is provided. The execution circuitry is to execute a single instruction to, for each result packed data element: preserve an existing value of the result packed data element or set the result packed data element to zero if a corresponding bit value in a writemask register is set to a first value; and if the corresponding bit value in the writemask register is set to a second value, then: multiply a first number of a first source packed data elements with corresponding packed data elements of a second source packed data elements to produce a first number of products, add the first number of products to a corresponding packed data element from a third source packed data elements to produce the result packed data element of a second size in a corresponding position in a source/destination packed data register.
Bibliography:Application Number: EP20220203441