LARGE PANEL DISPLAYS WITH REDUCED ROUTING LINE RESISTANCE
An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gat...
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Main Authors | , , , , , , , |
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Format | Patent |
Language | English French German |
Published |
30.11.2022
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Subjects | |
Online Access | Get full text |
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Summary: | An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates. |
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Bibliography: | Application Number: EP20210713310 |