WAFER CONVEYANCE UNIT AND WAFER CONVEYANCE METHOD

A failure analysis unit is a wafer conveyance unit configured to convey a wafer while holding the wafer in a semiconductor failure analysis apparatus, the wafer conveyance unit including: a placement table configured to fix a wafer at a predetermined observation position; and a wafer chuck configure...

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Bibliographic Details
Main Authors SHIMASE, Akira, ISHIZUKA, Toshimichi, IKESU, Masataka
Format Patent
LanguageEnglish
French
German
Published 24.01.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A failure analysis unit is a wafer conveyance unit configured to convey a wafer while holding the wafer in a semiconductor failure analysis apparatus, the wafer conveyance unit including: a placement table configured to fix a wafer at a predetermined observation position; and a wafer chuck configured to convey the wafer while holding the wafer to the observation position. The wafer chuck includes a plurality of holding members (protruding portions) provided so as to face a side surface of the wafer, and holds the wafer by sandwiching a peripheral portion of the wafer W with the plurality of holding members.
Bibliography:Application Number: EP20200914993