HARDWARE ALGORITHM FOR COMPLEX-VALUED EXPONENTIATION AND LOGARITHM USING SIMPLIFIED SUB-STEPS

A method of generating complex exponentiation and logarithms in hardware is described that uses half the number of bits of lookup tables as the state-of-the-art. By splitting up each of the iterations into more simplified stages or using more iterations, the amount of precomputed information that mu...

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Bibliographic Details
Main Author LONG, Benjamin John Oliver
Format Patent
LanguageEnglish
French
German
Published 17.08.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method of generating complex exponentiation and logarithms in hardware is described that uses half the number of bits of lookup tables as the state-of-the-art. By splitting up each of the iterations into more simplified stages or using more iterations, the amount of precomputed information that must be held by the circuitry is reduced. This allows synthesis tools to take this more succinct logical description of the algorithm and make it into efficient gate level logic for fabrication into more compact integrated circuitry.
Bibliography:Application Number: EP20200793109