HARDWARE QUEUE SCHEDULING FOR MULTI-CORE COMPUTING ENVIRONMENTS

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the secon...

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Bibliographic Details
Main Authors PALERMO, Stephen, MANGAN, John, KHADE, Abhishek, MAINI, Sarita, MCDONNELL, Niall, HIREMATH, Chetan, SHAH, Rahul, GANGULI, Mrittika, BURROUGHS, William, RICHARDSON, Bruce, SHAH, Shrikant, SONNIER, David, CHADDICK, Bradley, MOSUR, Praveen, LAYEK, Abhirupa, EADS, Gage, VERPLANKE, Edwin
Format Patent
LanguageEnglish
French
German
Published 08.03.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.
Bibliography:Application Number: EP20200863993