SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE MANUFACTURING METHOD, AND ELECTRONIC DEVICE

To arrange a protective material horizontally with respect to a substrate plane without the protective material coming into contact with wires in a wire-bonded semiconductor package.The semiconductor package includes a protective material, a substrate, bumps, and a semiconductor chip. The bumps are...

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Bibliographic Details
Main Author KANATAKE, Mitsuhito
Format Patent
LanguageEnglish
French
German
Published 23.03.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:To arrange a protective material horizontally with respect to a substrate plane without the protective material coming into contact with wires in a wire-bonded semiconductor package.The semiconductor package includes a protective material, a substrate, bumps, and a semiconductor chip. The bumps are provided on a chip plane of the semiconductor chip and are connected to the substrate via wires. The semiconductor chip is laminated on the substrate. A support is provided on the chip plane to support the protective material at a position where the height from the chip plane of the semiconductor chip is higher than the bumps.
Bibliography:Application Number: EP20200806121