PATTERNED WAFER SOLDER DIFFUSION BARRIER

Methods and apparatus for an integrated circuit having with a frontside metal layer on the frontside of the substrate and a backside metal layer on the backside of the substrate. The backside metal layer is deposited onto the backside of the substrate and into the via such that a portion of the back...

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Bibliographic Details
Main Author DUVAL, Paul J
Format Patent
LanguageEnglish
French
German
Published 09.02.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods and apparatus for an integrated circuit having with a frontside metal layer on the frontside of the substrate and a backside metal layer on the backside of the substrate. The backside metal layer is deposited onto the backside of the substrate and into the via such that a portion of the backside metal layer is connected to a portion of the frontside metal layer. A diffusion barrier layer is deposited on the backside metal layer located in the via.
Bibliography:Application Number: EP20200713795