DISAGGREGATION OF SOC ARCHITECTURE

The present disclosure provides an apparatus comprising a package assembly that includes a first base chiplet, a first logic chiplet stacked on the first base chiplet, a first interconnect structure to couple the cluster of compute units to the first interconnect fabric, a second base chiplet couple...

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Bibliographic Details
Main Authors TESHOME, Melaku, XAVIER, Binoj, FINLEY, Eric, GEORGE, Varghese, JAHAGIRDAR, Sanjeev, MASTRONARDE, Josh, CHENEY, Lance, KOKER, Altug, VEMULAPALLI, Vikranth, STRIRAMASSARMA, Lakshminarayanan, MATAM, Naveen, RAJWANI, Iqbal
Format Patent
LanguageEnglish
French
German
Published 19.01.2022
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:The present disclosure provides an apparatus comprising a package assembly that includes a first base chiplet, a first logic chiplet stacked on the first base chiplet, a first interconnect structure to couple the cluster of compute units to the first interconnect fabric, a second base chiplet coupled to the first base chiplet by a second interconnect structure, a second logic chiplet stacked on the second base chiplet, and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric. In the provided apparatus, the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets.
Bibliography:Application Number: EP20200709367