METHODS AND APPARATUS FOR DATA SYNCHRONIZATION IN SYSTEMS HAVING MULTIPLE CLOCK AND RESET DOMAINS

A data synchronization unit including first flip-flops (714), operating on a first clock domain (705) and a reset of a second clock domain (707), sampling data (D_SRC) from the first clock domain (705); a second flip-flop (716), operating in the first clock domain (705), sampling a request signal (R...

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Bibliographic Details
Main Author AGARWAL, Samiksha
Format Patent
LanguageEnglish
French
German
Published 10.11.2021
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:A data synchronization unit including first flip-flops (714), operating on a first clock domain (705) and a reset of a second clock domain (707), sampling data (D_SRC) from the first clock domain (705); a second flip-flop (716), operating in the first clock domain (705), sampling a request signal (REQ) when enabled by a request pulse (REQ_PULSE); a request signal path (726) configured to delay the request signal (REQ) by a first delay and to generate an enable signal (ENP) for recirculation multiplexers (722) in accordance with the delayed request signal; a reset signal synchronization path (736) configured to delay the reset signal (RST_B) of the first clock domain (705) by a second delay, wherein the second delay is shorter than the first delay; and multiplexers (734) having first inputs for receiving outputs of the recirculation multiplexers (722), a second input for receiving a reset value (RST B) of a programmable register, the multiplexers (734) being configured to selectively output signals at inputs to outputs.
Bibliography:Application Number: EP20210171144