FORCING CORE LOW POWER STATES IN A PROCESSOR

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power ma...

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Bibliographic Details
Main Authors Chu, Allen, Sistla, Krishnakanth, Varma, Ankush, Steiner, Ian
Format Patent
LanguageEnglish
French
German
Published 20.12.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed
Bibliography:Application Number: EP20210171073