METHOD OF DEADLOCK DETECTION AND SYNCHRONIZATION-AWARE OPTIMIZATIONS ON ASYNCHRONOUS PROCESSOR ARCHITECTURES

A method for improving the performance of applications executed within asynchronous processor architectures. In an embodiment, a method for improving execution time of compiled synchronized source code on an asynchronous processor architecture includes receiving, by a processing system, synchronized...

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Bibliographic Details
Main Authors GAO, Yaoqing, RODRIGUES, Christopher, ELTANTAWY, Ahmed, HAI, Lijuan
Format Patent
LanguageEnglish
French
German
Published 09.06.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for improving the performance of applications executed within asynchronous processor architectures. In an embodiment, a method for improving execution time of compiled synchronized source code on an asynchronous processor architecture includes receiving, by a processing system, synchronized source code comprising synchronization instructions to synchronize execution of the synchronized source code on different pipelines of the asynchronous processor architecture. The method also includes analyzing, by the processing system, the synchronized source code to determine whether the synchronized source code includes a broken code condition. The method also includes, after determining, by the processing system, that the synchronized source code does not include a broken code condition, outputting an optimized synchronized source code generated by performing a corrective action on the synchronized source code to correct a synchronization inaccuracy, inconsistency, or inefficiency in the synchronized source code.
Bibliography:Application Number: EP20180923057