SHARED MEMORY MESH FOR SWITCHING

Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive opera...

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Bibliographic Details
Main Authors PAPADANTONAKIS, Karl, DAMA, Jonathan, SOUTHWORTH, Robert, MCCORMICK, Jim, PENARANDA CEBRIAN, Roberto, SRINIVASAN, Arvind, HUGGAHALLI, Ramakrishna, NAEIMI, Helia
Format Patent
LanguageEnglish
French
German
Published 30.12.2020
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.
Bibliography:Application Number: EP20200164686