APPARATUSES, METHODS, AND SYSTEMS FOR MEMORY INTERFACE CIRCUIT ARBITRATION IN A CONFIGURABLE SPATIAL ACCELERATOR

Systems, methods, and apparatuses relating to arbitration among a plurality of memory interface circuits in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (...

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Bibliographic Details
Main Authors Daya, Bhavya K, ChoFleming, Kermin, Vinod, Krishna N, Suprun, Alexey, Kakade, Aniket S, Zou, Ping, Kaushikkar, Sujoyita
Format Patent
LanguageEnglish
French
German
Published 30.12.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:Systems, methods, and apparatuses relating to arbitration among a plurality of memory interface circuits in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for improved memory sub-system design via arbitration and the improvements to arbitration discussed herein.
Bibliography:Application Number: EP20200164075