WAFER PACKAGE DEVICE

A chip package device is provided. The chip package device includes a chip, and a first substrate and a second substrate that are disposed opposite to each other, where the chip is disposed on a surface that is of the first substrate and that faces the second substrate; the chip is electrically conn...

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Bibliographic Details
Main Authors TANG, Jiajie, YE, Guanhong, LIN, Laicun, LIU, Guowen, ZHANG, Huafeng, ZHENG, Shuai
Format Patent
LanguageEnglish
French
German
Published 06.01.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A chip package device is provided. The chip package device includes a chip, and a first substrate and a second substrate that are disposed opposite to each other, where the chip is disposed on a surface that is of the first substrate and that faces the second substrate; the chip is electrically connected to the first substrate through a first conductive part; the first substrate is electrically connected to the second substrate through a second conductive part; and a heat dissipation passage is formed between the chip and the second substrate through a thermally conductive layer. The chip package device further includes a molding compound that is configured to wrap the chip. The thermally conductive layer disposed between the chip and the second substrate can quickly dissipate a large amount of heat generated by the chip to the second substrate, so that the chip maintains a normal temperature.
Bibliography:Application Number: EP20190741747