STORAGE APPARATUS AND METHOD FOR ADDRESS SCRAMBLING

• Main Authors: XIA, Baolin, GU, Yucan, GU, Haiming, WU, Youfei
• Format: Patent
• Language: English; French; German
• Published: 16.12.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION; WIRELESS COMMUNICATIONS NETWORKS

A storage apparatus and method for address scrambling. The apparatus includes: a key-generating module (11) configured to generate a random key; a non-volatile key memory (12) configured to store the random key generated by the key-generating module (11); a key-reading module (13) configured to automatically read the random key stored in the non-volatile key memory (12) and store the random key; a memory control module (15) configured to output, to an address scrambling module (14), an unscrambled address in generated sequential control logic for reading or writing an on-chip memory; and the address scrambling module (14) connected to the memory control module (15), the key-reading module (13), and the memory (16), respectively, and configured to perform, according to the random key read by the key-reading module (13), scrambling processing on the unscrambled address outputted by the memory control module (15) to form a scrambled address, and send the scrambled address to the memory (16). The apparatus can implement scrambling processing on a data address without affecting the efficiency of reading or writing a memory, thus ensuring efficient and secure data reading and writing.