RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN STATE
A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indi...
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| Main Authors | , , |
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| Format | Patent |
| Language | English French German |
| Published |
04.08.2021
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry. |
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| AbstractList | A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry. |
| Author | WALKER, William L GOLDEN, Michael L EVERS, Marius |
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| DocumentTitleAlternate | RÉTENTION D'ENTRÉES DE MÉMOIRE CACHE D'UN COEUR DE PROCESSEUR PENDANT UN ÉTAT HORS TENSION RÜCKHALTUNG VON CACHE-EINTRÄGEN EINES PROZESSORKERNS WÄHREND EINES ABSCHALTZUSTANDS |
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| Notes | Application Number: EP20180874462 |
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| RelatedCompanies | Advanced Micro Devices, Inc |
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| Snippet | A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first... |
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| SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| Title | RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN STATE |
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