RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN STATE

A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indi...

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Bibliographic Details
Main Authors WALKER, William L, GOLDEN, Michael L, EVERS, Marius
Format Patent
LanguageEnglish
French
German
Published 04.08.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
Bibliography:Application Number: EP20180874462