PERIPHERAL BASED MEMORY SAFETY SCHEME FOR MULTI-CORE PLATFORMS
A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English French German |
Published |
08.11.2023
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds. |
---|---|
Bibliography: | Application Number: EP20190200630 |