SPUR FREQUENCY ESTIMATION INSIDE DIGITAL PHASE LOCKED LOOP

Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received...

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Bibliographic Details
Main Authors AVIVI, Rotem, DGANI, Yair, KERNER, Michael
Format Patent
LanguageEnglish
French
German
Published 08.04.2020
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Summary:Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.
Bibliography:Application Number: EP20170728989