DEVICE LAYER INTERCONNECTS
Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the dev...
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Main Authors | , , |
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Format | Patent |
Language | English French German |
Published |
06.11.2024
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Subjects | |
Online Access | Get full text |
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Summary: | Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array. |
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Bibliography: | Application Number: EP20190170433 |