PLACEMENT AND ROUTING OF CELLS USING CELL-LEVEL LAYOUT-DEPENDENT STRESS EFFECTS

Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place-and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information abou...

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Bibliographic Details
Main Author MOROZ, Victor
Format Patent
LanguageEnglish
French
German
Published 20.01.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place-and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information about dependency of each cell on hypothetical boundary conditions that can be imposed on the cell by any stress source originating in the vicinity of said cell in the layout. In order to select a cell for a target location in the layout, boundary conditions imposed on the target position by each of the cells neighboring the target position are determined. The system then selects an appropriate target cell in dependence upon the determined boundary conditions and the performance of the cell based on the boundary conditions imposed on the cell by the neighboring cells from the cell library.
Bibliography:Application Number: EP20180791612