GATE STACK FOR HETEROSTRUCTURE DEVICE

A heterostructure semiconductor device includes a first active layer (102) and a second active layer (106) disposed on the first active layer. A two-dimensional electron gas layer (104) is formed between the first and second active layers. A sandwich gate dielectric layer structure (113) is disposed...

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Bibliographic Details
Main Author Ramdani, Jamal
Format Patent
LanguageEnglish
French
German
Published 08.05.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A heterostructure semiconductor device includes a first active layer (102) and a second active layer (106) disposed on the first active layer. A two-dimensional electron gas layer (104) is formed between the first and second active layers. A sandwich gate dielectric layer structure (113) is disposed on the second active layer. A passivation layer (114) is disposed over the sandwich gate dielectric layer structure. A gate (116) extends through the passivation layer to the sandwich gate dielectric layer structure. First (118) and second (120) ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.
Bibliography:Application Number: EP20180199806