BINARY TRANSLATION SUPPORT USING PROCESSOR INSTRUCTION PREFIXES

A processing system implementing techniques for binary translation support using processor instruction prefixes is provided. In one embodiment, the processing system includes a register bank having a plurality of registers to store data for use in executing instructions and a processor core coupled...

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Bibliographic Details
Main Authors SONDAG, Tyler N, MARGULIS, Oleg, AGRON, Jason M
Format Patent
LanguageEnglish
French
German
Published 14.11.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processing system implementing techniques for binary translation support using processor instruction prefixes is provided. In one embodiment, the processing system includes a register bank having a plurality of registers to store data for use in executing instructions and a processor core coupled to the register bank. An instruction to be executed by the processor core is received. The instruction is associated with a binary translator operation to translate input instruction sequences to output instruction sequences. An opcode prefix referencing an extended register of the plurality of registers to be used during the binary translator operation. The extended register preserves a source register value of the plurality of registers.
Bibliography:Application Number: EP20160884152