INCREASING THREAD PAYLOAD FOR 3D PIPELINE WITH WIDER SIMD EXECUTION WIDTH

Reducing SIMD fragmentation for SIMD execution widths of 32 or even 64 channels in a single hardware thread leads to better EU utilization. Increasing SIMD execution widths to 32 or 64 channels per thread, enables handling more vertices, patches, primitives and triangles per EU hardware thread. Modi...

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Bibliographic Details
Main Authors RAOUX, Thomas F, LUEH, Guei-Yuan, MAIYURAN, Maiyuran, VENKATESH, Jayashree, CHEN, Gang
Format Patent
LanguageEnglish
French
German
Published 31.10.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Summary:Reducing SIMD fragmentation for SIMD execution widths of 32 or even 64 channels in a single hardware thread leads to better EU utilization. Increasing SIMD execution widths to 32 or 64 channels per thread, enables handling more vertices, patches, primitives and triangles per EU hardware thread. Modified 3D pipeline shader payloads can handle multiple patches in case of domain shaders or multiple primitives when primitive object instance count is greater than one in the case of geometry shaders and multiple triangles in case of pixel shaders.
Bibliography:Application Number: EP20160879654