REFRESH TIMER SYNCHRONIZATION BETWEEN MEMORY CONTROLLER AND MEMORY

A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

Saved in:
Bibliographic Details
Main Authors JOSE, Edwin, DROP, Michael
Format Patent
LanguageEnglish
French
German
Published 26.06.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.
Bibliography:Application Number: EP20160759956