POWER MANAGEMENT WITH FLIP-FLOPS

An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes...

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Bibliographic Details
Main Authors BHAN, Divjyot, PANT, Harshat, CAO, Lipeng, KOCHURI, Sai Pradeep, NAJDESAMII, Parissa, VILANGUDIPITCHAI, Ramaprasath
Format Patent
LanguageEnglish
French
German
Published 07.04.2021
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.
Bibliography:Application Number: EP20160763124