MEMORY CELL WITH DIFFERENT PROGRAM AND READ PATHS FOR ACHIEVING HIGH ENDURANCE

A memory cell (100) includes a coupling device (CD), a read transistor (RT), a first read selection transistor (RST1), a second read selection transistor (RST2), an erase device (ED), a program transistor (PT), and a program selection transistor (PST) . The coupling device (CD) is formed on a first...

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Bibliographic Details
Main Authors Lo, Chun-Yuan, Chang, Wei-Chen, Wang, Shih-Chen
Format Patent
LanguageEnglish
French
German
Published 06.06.2018
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory cell (100) includes a coupling device (CD), a read transistor (RT), a first read selection transistor (RST1), a second read selection transistor (RST2), an erase device (ED), a program transistor (PT), and a program selection transistor (PST) . The coupling device (CD) is formed on a first doped region (Reg1). The erase device (ED) is formed on a second doped region (Reg2). The read transistor (RT), the first read selection transistor (RST1), the second read selection transistor (RST2), the program transistor (PT), and the program selection transistor (PST) are formed on a third doped region (Reg3). A gate terminal of the coupling device (CD) is coupled to a common floating gate. A gate terminal of the erase device (ED) is coupled to the floating gate. During a program operation, electrical charges are moved to the common floating gate. During an erase operation, electrical charges are ejected from the common floating gate to the erase device (ED).
Bibliography:Application Number: EP20160203971