MASKING A POWER STATE OF A CORE OF A PROCESSOR

In one embodiment, a processor comprises a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic includes a fabric interface logic having a first storage to store state information of the core when the core is in a low power state. The core perimeter l...

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Bibliographic Details
Main Authors SISTLA, Krishnakanth V, HALLNOR, Erik G, WEIER, Kimberly C, GARG, Vivek, MULLA, Dean, CHOUBAL, Ashish V, GENDLER, Alexander, NOVAKOVSKY, Larisa
Format Patent
LanguageEnglish
French
German
Published 17.05.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In one embodiment, a processor comprises a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic includes a fabric interface logic having a first storage to store state information of the core when the core is in a low power state. The core perimeter logic is to enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. The fabric interface logic includes a snoop logic to receive a snoop request from a requester when the core is in the low power state and send a snoop response to the requester while the core is to remain in the low power state.
Bibliography:Application Number: EP20160830980