LOW-FLOW AND LOW-NOISE DETECTION CIRCUIT

The detection circuit comprises a detector connected to an integration node. A bias circuit biases the detector between a first bias state and a second floating state. The potential of the integration node is at a target value when the bias circuit biases the detector to the first state and varies w...

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Bibliographic Details
Main Authors AUFRANC, Sébastien, SANSON, Eric
Format Patent
LanguageEnglish
French
German
Published 11.09.2019
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Summary:The detection circuit comprises a detector connected to an integration node. A bias circuit biases the detector between a first bias state and a second floating state. The potential of the integration node is at a target value when the bias circuit biases the detector to the first state and varies when the detector is in floating state. A measurement circuit without charge losses delivers a value representative of the potential present on the integration node N. A transfer circuit of the electric charges performs transfer of the electric charges from a stray capacitor of the photodiode to an integration capacitor. An output terminal delivers a voltage representative of the potential present on the second terminal of the first capacitor.
Bibliography:Application Number: EP20170201545