DEVICE AND PROCESSING ARCHITECTURE FOR INSTRUCTION MEMORY EFFICIENCY

Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruc...

Full description

Saved in:
Bibliographic Details
Main Authors VINCENT, John Edward, WATSON, Benton, SINN, Peter Man Kin
Format Patent
LanguageEnglish
French
German
Published 18.07.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.
Bibliography:Application Number: EP20160838284