LOW POWER HIGH SPEED RECEIVER WITH REDUCED DECISION FEEDBACK EQUALIZER SAMPLERS

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with...

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Bibliographic Details
Main Authors MUSAH, Tawfiq, VENKATRAM, Hariprasath, CASPER, Bryan K
Format Patent
LanguageEnglish
French
German
Published 23.01.2019
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.
Bibliography:Application Number: EP20160759234