LOW DROP OUT COMPENSATION TECHNIQUE FOR REDUCED DYNAMIC ERRORS IN DIGITAL-TO-TIME CONVERTERS

An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitr...

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Bibliographic Details
Main Authors GORDON, Eshel, DEGANI, Ofir, SIEVERT, Sebastian
Format Patent
LanguageEnglish
French
German
Published 18.04.2018
Subjects
CONTROLLING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PHYSICS
REGULATING
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
TRANSMISSION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.
Bibliography:Application Number: EP20170177264