INSTRUCTIONS CONTROLLING ACCESS TO SHARED REGISTERS OF A MULTI-THREADED PROCESSOR

Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded pro...

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Bibliographic Details
Main Authors MESH, Alexander, SLEGEL, Timothy, BIRAN, Giora, BUSABA, Fadi, Yusuf, FARRELL, Mark, EREZ, Ophir, HELLER, Lisa, JACOBI, Christian
Format Patent
LanguageEnglish
French
German
Published 16.03.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.
Bibliography:Application Number: EP20150787164