APPARATUS AND ASSOCIATED METHOD

A semiconductor arrangement comprising; a normally-on transistor (101) having first and second main terminals and a control terminal, a normally-off transistor (105) having first and second main terminals and a control terminal, the transistors connected in a cascode arrangement by a connection (112...

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Bibliographic Details
Main Authors Wynne, Barry, Gajda, Mark Andrzej
Format Patent
LanguageEnglish
French
German
Published 11.03.2020
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:A semiconductor arrangement comprising; a normally-on transistor (101) having first and second main terminals and a control terminal, a normally-off transistor (105) having first and second main terminals and a control terminal, the transistors connected in a cascode arrangement by a connection (112) between one of the main terminals of the normally-on transistor (101) and one of the main terminals of the normally-off transistor (105), a current-source arrangement (113) connected to a node (112) on the connection and configured to provide for control of the voltage at said node between the normally-on (101) and normally-off (105) transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor (101) formed therein and a second semiconductor die having the normally-off transistor (105) formed therein, the current-source arrangement (113) formed in the first and/or second semiconductor dies.
Bibliography:Application Number: EP20160151746