DETECTION OF DISASSEMBLY OF MULTI-DIE CHIP ASSEMBLIES

• Main Authors: SHEN-ORR, Chaim D, BEAR, Uri, AMARILIO, Lior
• Format: Patent
• Language: English; French; German
• Published: 28.06.2017
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

A multi-die chip assembly is described, the multi-die chip assembly including at least one detection apparatus which detects manipulations of the multi-die chip assembly, the detection apparatus including a distributed circuit including a circuit whose elements are distributed among those dies which include the elements of a local reference circuit, the distributed circuit including a free running clock, at least one local reference circuit disposed in at least one die of the multi-die chip assembly, each of the local reference circuits including a free running clock, and at least one non-volatile memory, in which is stored during manufacture of the multi-die chip assembly, an allowed range of a result of a function having at least two arguments for each reference circuit a value of the frequency of the local reference circuit as manufactured, and a value of the frequency of the distributed circuit as manufactured, at least one element of the plurality of memories being disposed in each die including the elements of the local reference circuit. Related methods, apparatus, and systems are also described.