INTEGRATED CIRCUIT WITH DISTRIBUTED CLOCK TAMPERING DETECTORS

A circuit configuration for secure application includes several internal frequency detectors (10) arranged in digital units at critical points of an integrated circuit (30). The clock detectors (10) are concealed in the digital part of the integrated circuit (30) each as a standard cell (flip-flop u...

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Bibliographic Details
Main Author WALTER, FABRICE
Format Patent
LanguageEnglish
French
German
Published 10.02.2016
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:A circuit configuration for secure application includes several internal frequency detectors (10) arranged in digital units at critical points of an integrated circuit (30). The clock detectors (10) are concealed in the digital part of the integrated circuit (30) each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors (10) are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.
Bibliography:Application Number: EP20150177804