INTEGRATED CLOCK DIFFERENTIAL BUFFERING

A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal and generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal and to generate a...

Full description

Saved in:
Bibliographic Details
Main Authors BODDU, VIJAYA K, HUANG, CHOUPIN, RUSU, STEFAN, PETERSON, NICHOLAS B
Format Patent
LanguageEnglish
French
German
Published 20.01.2016
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
Online AccessGet full text

Cover

More Information
Summary:A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal and generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal and to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and provide a first differential reference clock signal corresponding. A second set of clock signal output buffers is coupled to receive the second reference clock signal and provide a second differential reference clock signal. The first and second PLL circuits, and the first and second sets of output buffers reside within an integrated circuit package having a die to receive at least the first differential reference clock signal.
Bibliography:Application Number: EP20140770873