PROGRAMMABLE CPU REGISTER HARDWARE CONTEXT SWAP MECHANISM

A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the sw...

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Bibliographic Details
Main Authors KANELLOPOULOS, Joseph, CATHERWOOD, Michael, I, MICKEY, David, KRIS, Bryan
Format Patent
LanguageEnglish
French
German
Published 20.05.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
Bibliography:Application Number: EP20140716090