LOW POWER STATIC RANDOM ACCESS MEMORY

A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the...

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Bibliographic Details
Main Authors HARRIS, Micky, KHALED, Wasim
Format Patent
LanguageEnglish
French
German
Published 25.09.2019
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.
Bibliography:Application Number: EP20140704013