Latch circuit

A latch circuit is based on a master-slave cross-coupled inverter pair (40) configuration. The inverters (0, 62) of the slave circuit (42) are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the v...

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Bibliographic Details
Main Authors Kapoor, Ajay, Sharma, Vibhu, Malzahn, Ralf
Format Patent
LanguageEnglish
French
German
Published 05.08.2020
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:A latch circuit is based on a master-slave cross-coupled inverter pair (40) configuration. The inverters (0, 62) of the slave circuit (42) are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element (64, 66). This circuit design avoids the need for an internal clock-buffer and enables single phase clocking (CK), and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input (DIN) and the output data signal (DOUT) is same.
Bibliography:Application Number: EP20130191288